1. Field
Embodiments of the present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a conductive path provided to electrically connect an upper and lower portion of the semiconductor package.
2. Description of the Related Art
As semiconductor chip manufacturing process have continuously been developed, sizes of semiconductor chip have been reduced. Currently, due to the dramatic reduction in sizes of semiconductor chips, cases in which a package size needs to be increased for an electrical connection when a semiconductor package is formed are occurring. One semiconductor packaging technique that was proposed in this development process is a pan-out package.
Also, many types of techniques in which a pattern structure for vertically transferring a signal is formed at an outer area of the pan-out package, and packages of the same kind or a different kind are vertically stacked to expand a memory capacity or to enhance operation performance of a semiconductor are also being developed.
A pan-out package has an embedded structure in which a semiconductor chip is mounted inside a circuit board, or a structure in which a solder ball is disposed as a final input/output terminal of the semiconductor chip at an outer surface of the semiconductor chip. In general, a via-hole is formed in a substrate to provide a conductive path for electrically connecting upper and lower portions of a semiconductor package, and a metal redistribution layer is formed to electrically connect the via-hole with the semiconductor chip.
In the case of a conventional pan-out package having a via-hole, to connect a pad of the semiconductor chip with the via-hole, a metal pad is formed on an upper surface of the substrate in which the via-hole is formed, and the metal pad is also formed on a lower surface of the substrate to connect an external substrate with the via-hole. Also, a first insulating layer is formed on the metal pad of the upper surface of the substrate, the pad of the semiconductor chip is electrically connected with the via-hole through the metal redistribution layer, and then a second insulating layer is coated thereon.
However, in such a structure, since the metal pad formed on the upper surface of the substrate has a step of a predetermined thickness or more, the first insulating layer should be coated more thickly than the metal pad to uniformly form the first insulating layer. Since the insulating is formed thickly, there is a limit in selecting an insulating material, and fine pitch patterning also faces limitations.
Korean Patent No. 10-1362714 (published on Feb. 13, 2014) discloses a semiconductor package including a through-wire which passes through an insulating substrate, and a manufacturing method thereof.
An embodiment of the present invention relates to a semiconductor package which can be manufactured in a thin type and a method of manufacturing the same.
Further, the embodiment of the present invention relates to a semiconductor package in which a wiring layer can be stacked without an additional metal pad between a through wiring to pass through a substrate and a wiring layer and a method of manufacturing the same.